aigverse.io¶
Provides file import and export functions for logic networks.
The module contains readers and writers for common file formats in the domain.
Module Contents¶
- read_aiger_into_aig(filename: str | PathLike) NamedAig¶
Reads a binary AIGER file into a logic network.
- Parameters:
filename – Path to the AIGER file.
- Returns:
The parsed network instance.
- Raises:
RuntimeError – If parsing the AIGER file fails.
- read_ascii_aiger_into_aig(filename: str | PathLike) NamedAig¶
Reads an ASCII AIGER file into a logic network.
- Parameters:
filename – Path to the ASCII AIGER file.
- Returns:
The parsed network instance.
- Raises:
RuntimeError – If parsing the ASCII AIGER file fails.
- read_aiger_into_sequential_aig(filename: str | PathLike) SequentialAig¶
Reads a binary AIGER file into a logic network.
- Parameters:
filename – Path to the AIGER file.
- Returns:
The parsed network instance.
- Raises:
RuntimeError – If parsing the AIGER file fails.
- read_ascii_aiger_into_sequential_aig(filename: str | PathLike) SequentialAig¶
Reads an ASCII AIGER file into a logic network.
- Parameters:
filename – Path to the ASCII AIGER file.
- Returns:
The parsed network instance.
- Raises:
RuntimeError – If parsing the ASCII AIGER file fails.
- write_aiger(ntk: Aig, filename: str | PathLike) None¶
Writes a logic network to a binary AIGER file.
- Parameters:
ntk – The network to serialize.
filename – Destination path for the AIGER file.
- read_pla_into_aig(filename: str | PathLike) Aig¶
Reads a PLA file into a logic network.
- Parameters:
filename – Path to the PLA file.
- Returns:
The parsed network instance.
- Raises:
RuntimeError – If parsing the PLA file fails.
- read_verilog_into_aig(filename: str | PathLike) NamedAig¶
Reads a synthesized gate-level Verilog netlist into a logic network.
- Parameters:
filename – Path to the Verilog file.
- Returns:
The parsed network instance.
- Raises:
RuntimeError – If parsing the Verilog file fails.